1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device with a reduced asynchronous access time (tAA).
2. Description of the Related Art
As a semiconductor device has various functions, cases where a memory device is built in a semiconductor device are being increased, and as data to be processed by the semiconductor device are increased, the memory capacity is also being increased. With an increment of the memory capacity, a redundancy memory cell for replacing a defective memory cell is increasingly used.
A repairing task of a semiconductor memory device using the redundancy memory cell is performed such that a redundancy row and a redundancy column are formed in advance per a certain memory cell array, and a row or column having a defective memory cell is replaced with the redundancy row or the redundancy column. For example, if a defective memory cell is found by a test after a wafer processing, a program operation for replacing a corresponding address with an address of a redundancy memory cell is performed in an internal circuit. Thus, if an address signal corresponding to a defective line is inputted when the semiconductor device operates, a redundancy line instead of the defective line is accessed.
The typical repairing task uses fuses. As such a repairing technique, there is a technique for replacing a row or column having the defective memory cell with a redundancy row or redundancy column, such as a technique of installing the fuses in an internal circuit for repairing task, and then applying an over current to the fuse located on the line connected to a row or column having the defective memory cell so as to blow out the fuse, a technique of blowing out the fuse by a laser beam, a technique of connecting junction portions by a laser beam, and a programming technique using an EPROM.
Typically, the semiconductor memory device decodes an address applied from an external portion to select a corresponding memory cell for data input or output. The semiconductor memory device having the redundancy memory cell determines whether to use the redundancy memory cell before selecting the corresponding memory cell.
When a read or write command and a memory cell address are applied, an internal read or write command generated in the semiconductor memory device in response to the read or write command needs to be delayed during a time for decoding the address and determining whether to use the redundancy memory cell.
As representative semiconductor memory devices, there are a dynamic random access memory (DRAM) and a flash memory. Hereinafter, as an example of the semiconductor memory device, the DRAM is exemplarily explained.
Among DRAMs, a double data rate (DDR) memory device uses an additive latency concept. The additive latency is proposed in a DDR2 standard, and is referred to as the number of clocks to tRCD (RAS to CAS delay) from the time that a read/write command is inputted after an active state of a memory device. The tRCD is an amount of time until a time that a column address strobe (CAS) signal is inputted after a row address strobe signal (RAS) is inputted. The memory device becomes in an active state at a time that the RAS signal is inputted, and then the read/write command is inputted before a time that the CAS signal is inputted. At this time, a time when the CAS signal is inputted and the read/write command is executed from a moment that the read/write command is inputted is the additive latency.
For the read/write operation, the semiconductor memory device receives the read/write command and delays it during as a long time as the additive latency (AL), and then generates and outputs the internal read/write command. The synchronous memory device receives an active command, the read/write command, a pre-charge command for data access, and the additive latency is the amount of time that the read/write command is received faster than designated timing.
For example, if it is assumed that the additive latency is 2 (i.e., AL=2 clock cycles), when two clock cycles lapse after the read command is inputted to the memory device, the memory device performs an operation for generating an internal read command for the inputted read command. A synchronous memory device having no additive latency receives the read/write command to perform a corresponding data access operation when a time corresponding to tRCD lapses after the active command is inputted. However, a synchronous memory device having the additive latency receives the read/write command before a time of the additive latency, even though a time corresponding to tRCD has not lapsed after the active command is inputted.
FIG. 1 is a block diagram illustrating an address decoder of a conventional semiconductor memory device.
As described above, the defective memory cell is replaced in a row or column unit with the redundancy row or the redundancy column. Hereafter, the repairing operation is explained centering on the case where the column corresponding to the defective memory cell is replaced with the redundancy column.
If an internal read/write command MRW generated in the semiconductor memory device is applied in response to the column address CA and the read/write command, since the internal read/write command MRW should be delayed during a time when a redundancy fuse and decoder 20 decodes the column address CA and determines whether to use the redundancy memory cell, the internal read/write command MRW is delayed during a predetermined time by a delay portion 10 before being outputted as a final read/write command FRW.
The delay portion 10 can comprises even-number inverters. The delay time of the delay portion 10 for delaying the internal read/write command MRW to be outputted as the final read/write command FRW is set to be equal to a time that the redundancy fuse and decoder 20 decodes the column address and determines whether to use the redundancy memory cell.
In FIG. 1, the redundancy fuse and decoder 20 receives the column address CA to determine whether to use the redundancy column and decodes the column address CA to select a corresponding column. A state of the fuse, which is blown out or not, is determined using the repairing task described above. Thus, when the column address CA is applied, the redundancy fuse and decoder 20 outputs a redundancy selecting signal RED representing whether to use the redundancy memory cell according to the fuse state. If the redundancy memory cell is used, the redundancy fuse and decoder 20 decodes the column address CA and outputs a decoded column address DCA.
When the final read/write command FRW is applied to the column selecting portion 30, the column selecting portion 30 outputs the decoded column address DCA as a column selecting signal NCOL for selecting a normal column when it is determined that the redundancy memory cell is not used, or the column selecting portion 30 outputs a redundancy column selecting signal RCOL for selecting a redundancy column when it is determined that the redundancy memory is used, in response to the redundancy selecting signal RED outputted from the redundancy fuse and decoder 20.
Generally, a time that the delay portion 10 delays the internal read/write command MRW and outputs as the final read/write command FRW is about 0.5 ns to 1.0 ns, and this value is about 5 to 10% of the asynchronous access time tAA representing a time until data are outputted to the external portion from a time when the read/write command is applied from the external portion, resulting in a significant time loss.
In particular, in a case where the semiconductor memory device has a function such as the additive latency and the address is applied before the internal read/write command is generated, there occurs an unnecessary time loss in delaying the internal read/write command, since the process for decoding the address and determining whether to use the redundancy function is performed after the internal read/write command is generated even though the address is applied in advance. This serves to obstruct a high speed operation of the semiconductor memory device and lowers the efficiency.